Cedar™-HLS is a service for mapping from a high-level language (C/SystemC) to our technology. This service reduces the cost and work period for our customers.
Benefits of high level synthesis
- Reduced development period: the amount of description is reduced by one tenth and the verification time are reduced by one third (based on our results)
- Reusing of sources: the efficiency of development can be improved (ease of changing devices/technologies)
- Ease of evaluation: performance and footprint (cost) can easily be optimized using parameters
- Reusing of sources: the efficiency of development can be improved (ease of changing devices/technologies)
- Ease of evaluation: performance and footprint (cost) can easily be optimized using parameters
Example applications of Cedar™-HLS
- Optimal source code tuning for custom SoCs (source code rewriting)
- Confirmation of high level synthesis results and integrity by performing RTL logic synthesis
- Confirmation of high level synthesis results and integrity by performing RTL logic synthesis
| Service Category | Service Description | Item Submitted by Customer | Deliverable from Socionext (Example) |
|---|---|---|---|
| Handing off of RTL designed with high level synthesis RTL hand-off | Rewriting of a language in accordance with the tool Rewriting of a language in accordance with constraints |
Functional specifications Constraint conditions High level language |
Rewritten high level language Library for high level synthesis RTL designed with high level synthesis |
| Handing off of high level language | High level language is handed off and subsequent LSI design is performed under contract | (subject to the above described service) | LSI |
| Cedar™ coordination | High level synthesis of RTL for FPGA High level synthesis of RTL for ESL |
Functional specifications Constraint conditions High level language |
RTL SystemC |
